Method of forming an element of a microelectronic circuit

ABSTRACT

A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

BACKGROUND OF THE INVENTION

[0001] 1). Field of the Invention

[0002] This invention relates to a method of forming an element of amicroelectronic circuit and to a device that includes the element.

[0003] 2). Discussion of Related Art

[0004] Nanotechnology involves the formation of extremely smallstructures with dimensions on the order of nanometers in multipledirections.

[0005] Certain devices, for example, silicon on insulator (SOI) devices,require that a monocrystalline silicon or other monocrystallinesemiconductor material be formed on an insulating dielectric layer.Various techniques exist that can be used for creating a monocrystallinesemiconductor layer on an insulating layer. Such techniques usuallyinvolve the implantation of ions to a specific depth into amonocrystalline semiconductor material, attaching a dielectric layer ofanother wafer to the semiconductor material, subsequently shearing thesemiconductor material at a depth to which the ions are implanted,whereafter a thin layer of semiconductor material remains behind on thedielectric layer. A very thin and uniform semiconductor layer can so beformed on a dielectric layer.

[0006] Semiconductor fabrication environments, however, rarely makeprovision for attachment of wafers to one another and subsequentshearing of the wafers from one another, and are thus ill-equipped forthe manufacture of SOI devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is described by way of example with reference tothe accompanying drawings, wherein:

[0008]FIG. 1 is a perspective view illustrating a portion out of a waferincluding a monocrystalline substrate, a dielectric layer, and a thinand uniform sacrificial layer;

[0009]FIG. 2 is a view similar to FIG. 1 after a left portion of thesacrificial layer is etched away;

[0010]FIG. 3 is a view similar to FIG. 2 after a height-defining layeris formed;

[0011]FIG. 4 is a view similar to FIG. 3 after a left front portion ofthe height-defining layer and the dielectric layer are etched away toleave a nucleation site exposed on the monocrystalline substrate;

[0012]FIG. 5 is a view similar to FIG. 4 after the sacrificial layer isetched to leave a gap between the dielectric layer and a right portionof the height-defining layer;

[0013]FIG. 6 is a view similar to FIG. 5 after an initial portion of amonocrystalline semiconductor material is grown on the nucleation site;

[0014]FIG. 7 is a view similar to FIG. 6 after the monocrystallinesemiconductor material has grown to form a monocrystalline layer in thegap;

[0015]FIG. 8 is a view similar to FIG. 7 after a mask block is formed onthe right portion of the height-defining layer;

[0016]FIG. 9 is a view similar to FIG. 8 after the height-defining layeris etched with the mask block defining the dimensions of a spacer blockof the height-defining layer that remains on the monocrystalline layer;

[0017]FIG. 10 is a view similar to FIG. 9 after spacer side walls areformed adjacent opposing sides of the spacer block;

[0018]FIG. 11 is a view similar to FIG. 10 after the spacer block isetched away;

[0019]FIG. 12 is a view similar to FIG. 11 after the monocrystallinelayer is etched with the spacer side walls serving as a mask, so thatmonocrystalline wire elements of the monocrystalline layer remain on thedielectric layer;

[0020]FIG. 13 is a view similar to FIG. 12 after the spacer side wallsare etched away; and

[0021]FIG. 14 is a view similar to FIG. 13 illustrating the manufactureof a tri-gate transistor device that includes the wire elements.

DETAILED DESCRIPTION OF THE INVENTION

[0022] In the following description, terms such as horizontal, vertical,width, length, height, and thickness are used. These terms are used todescribe and define orientations of structures and surfaces relative toone another, and should not be interpreted as pertaining to an absoluteframe of reference.

[0023]FIG. 1 of the accompanying drawings illustrates a portion 20 outof a partially fabricated wafer, having a width 22 and a length 24. Theportion 20 includes a conventional silicon monocrystalline substrate 26,a supporting silicon dioxide (SiO₂) dielectric layer 28 formed on themonocrystalline substrate 26, and a silicon nitride (Si₂NO₃) sacrificiallayer 30 formed on the dielectric layer 28. The substrate may, forexample, be silicon (Si), germanium (Ge), silicon germanium(Si_(x)Ge_(y)), gallium arsenide (GaAs), InSb, GaP, GaSb, or carbon. Thesacrificial layer 30 has a thickness 34A which is extremely thin,typically on the order of a few nanometers. A process for forming 15 nmthin and uniform silicon nitride layers is, for example, plasma enhancedchemical vapor deposition (CVD) with power of 1 kW, a high frequency of13.5 MHz, or a low frequency of about 10 kHz with CVD conditions ofbetween 2 and 3 Torr, with temperature of 350-450° C., with silane flowrate of 75-150 sccm, a N₂O flow rate of 10-15 slm, and an N₂ flow rateof 20 slm.

[0024] As illustrated in FIG. 2, a portion of the sacrificial layer 30is subsequently removed. A remaining portion of the sacrificial layer 30now has a width 35 and a portion 36 of the dielectric layer is exposed.The portion 36 has a width 38 and extends across the length 24. A sidesurface 42 of the sacrificial layer 30 is exposed.

[0025] As illustrated in FIG. 3, a height-defining layer 44 issubsequently formed. The height-defining layer 44 is typically made ofthe same material as the dielectric layer 28. The height-defining layer44 has a left portion 46 on and structurally connected to the dielectriclayer 28, and a right portion 48 having a lower surface on an uppersurface of the sacrificial layer 30. A distance between a horizontalupper surface of the dielectric layer 28 and the horizontal lowersurface of the right portion 48 is defined by the thickness 34A of thesacrificial layer 30.

[0026]FIG. 4 illustrates the structure of FIG. 3 after a front of theleft portion 46 is removed. The entire structure of FIG. 3 is maskedwhile leaving an opening above the front of the left portion 46, andthen exposing the front of the left portion 46 to an etchant thatselectively removes the materials of the dielectric layer 28, thesacrificial layer 30, and the height-defining layer 44 over the materialof the monocrystalline substrate 26. The height-defining layer 44 isstill structurally connected through a rear portion 50 of the leftportion 46 to the dielectric layer 28 and the monocrystalline substrate26. The side surface 42 of the sacrificial layer 30 is exposed withinthe portion that has been etched out. A nucleation site 52 is exposed onthe monocrystalline substrate 26.

[0027] As illustrated in FIG. 5, the sacrificial layer 30 issubsequently etched away. An etchant is used that selectively removessome material of the sacrificial layer 30 over the materials of theother components illustrated in FIG. 4. The rear portion 50 suspends theright portion 48 above the dielectric layer 28. A gap 34B is definedbetween the upper surface of the dielectric layer 28 and the lowersurface of the right portion 48. The gap 54 has a vertical height 34Bthat equals the initial thickness 34A of the sacrificial layer 30.

[0028] The nucleation site 52 is cleaned in a hydrogen bake step at 200°C. for three minutes with an H₂ flow rate of 20 slm at 20 Torr.

[0029] As illustrated in FIG. 6, growth of monocrystalline semiconductormaterial 60 is then initiated on the nucleation site 52. Conventionalprocesses that are used for epitaxial growth of silicon may be used forselectively growing the monocrystalline semiconductor material 60, forexample, a CVD process is in an ASM E3000 epitaxial reactor at atemperature of 825° C., 240 sccm of SiH₂CL₂, 140 sccm HCl, and 20 slm ofhydrogen at a pressure of 20 Torr. The monocrystalline semiconductormaterial 60 grows from the nucleation site 52 vertically upward past aleft side surface of the dielectric layer 28. The precleaning of thenucleation site 52 together with the processing conditions ensure thatthe material 60 is monocrystalline and free of defects. What should benoted is that the gap 54 is open on a side of the monocrystallinesemiconductor material 60. As an alternative, Si_(x)Ce_(y) or anothermaterial may be used instead of silicon.

[0030] As illustrated in FIG. 7, the monocrystalline semiconductormaterial 60 subsequently grows from left to right horizontally throughthe gap 54. A thin monocrystalline layer 62 is so formed in the gap 54.The monocrystalline layer 62 has a thickness 34C that equals the height34B of the gap 54 and the initial thickness 34A of the sacrificial layer30. Because the sacrificial layer 30 is extremely thin and has a veryuniform thickness, the monocrystalline layer 62 is also extremely thinand has an extremely uniform thickness.

[0031] Referring to FIGS. 8 and 9, a mask block 64 is subsequentlypatterned on the right portion 48 (FIG. 8). The mask block 64 is thenused to pattern a spacer block 66 out of the height-defining layer 44,whereafter the mask block 64 is removed (FIG. 9). The spacer block 66has the same width and length as the mask block 64.

[0032] As illustrated in FIG. 10, silicon nitride spacer side walls 68are subsequently formed on opposing sides of the spacer block 66 and onthe upper surface of the monocrystalline layer 62. The spacer side walls68 are formed by depositing a silicon nitride layer conformally over themonocrystalline layer 62 and over opposing side and upper surfaces ofthe spacer block 66, whereafter the silicon nitride layer is etched backto the leave the spacer side walls 68. An etchant is used thatselectively removes silicon nitride over pure monocrystalline siliconand silicon dioxide. An advantage of such a process is that the spacerside walls 68 can be made extremely thin and uniform in thickness. Inthe given embodiment, therefore, the height-defining layer 44 serves thedual purpose of defining the vertical height 34B of the gap 54 out ofwhich the spacer block 66 is formed for purposes of defining thepositions of the spacer side walls 68.

[0033] As illustrated in FIG. 11, the spacer block 66 is subsequentlyremoved. An entire upper surface of the monocrystalline layer 62 is thenexposed, except directly below the spacer side walls 68. An etchant isused and selectively removes silicon dioxide over silicon nitride andpure monocrystalline silicon.

[0034] Referring to FIG. 12, exposed portions of the monocrystallinelayer 62 are removed by anisotropically etching the monocrystallinelayer 62, with the spacer side walls 68 serving as a mask. What remainsof the monocrystalline layer 62 are monocrystalline wire elements 72directly below the spacer side walls 68.

[0035] Referring to FIG. 13, the spacer side walls are subsequentlyremoved with an etchant that selectively removes silicon nitride overpure monocrystalline silicon and silicon dioxide. Upper surfaces of thewire elements 72 are then exposed. Heights of the wire elements 72 arethe same as the thickness of the initial sacrificial layer 30, and theirwidths are defined by the widths of the spacer side walls 68.

[0036] As illustrated in FIG. 14, the wire elements 72 may form part ofa tri-gate transistor device 74. Each semiconductor wire element 72 isfirst implanted with P- or N-dopants to make it conductive. A gatedielectric layer 76 is then formed on opposing side and an upper surfaceof each wire element 72. A conductive gate electrode 78 is thenmanufactured over upper and side surfaces of both gate dielectric layers76. The wire elements 72 are then annealed to activate the dopants. Avoltage can be applied over the wire elements 72. When a voltage isswitched on the gate electrode 78, current flows through the wireelements 72.

[0037] While certain exemplary embodiments have been described and shownin the accompanying drawings, it is to be understood that suchembodiments are merely illustrative and not restrictive of the currentinvention, and that this invention is not restricted to the specificconstructions and arrangements shown and described since modificationsmay occur to those ordinarily skilled in the art.

What is claimed:
 1. A method of forming an element of a microelectroniccircuit, comprising: forming a sacrificial layer having a lower surfaceon an upper surface of a support layer; forming a height-defining layerhaving a lower surface on an upper surface of the sacrificial layer;removing the sacrificial layer so that a gap is defined between theupper surface of the support layer and the lower surface of theheight-defining layer; and growing a monocrystalline semiconductormaterial from a nucleation site at least partially through the gap witha height of the semiconductor material being defined by a height of thegap.
 2. The method of claim 1, further comprising: removing theheight-defining layer; and patterning the semiconductor material.
 3. Themethod of claim 2, wherein the support layer is an insulator and thesemiconductor material is patterned into an elongate wire element. 4.The method of claim 3, further comprising: doping the wire element; andforming a conductive gate over and along opposing sides of the wireelement.
 5. The method of claim 1, wherein the semiconductor material isat least one of silicon (Si), germanium (Ge), silicon germanium(Si_(x)Ge_(y)), gallium arsenide (GaAs), InSb, GaP, GaSb and carbon. 6.The method of claim 1, further comprising: forming the support layerover a portion of a semiconductor monocrystalline substrate, an openportion of the semiconductor monocrystalline substrate having thenucleation site.
 7. A method of forming an element of a microelectroniccircuit, comprising: forming a dielectric layer on a semiconductormonocrystalline substrate; forming a structure on the semiconductormonocrystalline substrate, having a height-defining layer, a gap beingdefined between an upper surface of the support layer and a lowersurface of the height-defining layer; and growing a monocrystallinesemiconductor material from a nucleation site on the semiconductormonocrystalline substrate, the semiconductor material growing at leastpartially through the gap with a height of the semiconductor materialbeing defined by a height of the gap.
 8. The method of claim 7, furthercomprising: removing the height-defining layer; and patterning thesemiconductor material.
 9. The method of claim 8, wherein the supportlayer is an insulator and the semiconductor material is patterned intoan elongate wire element.
 10. The method of claim 9, further comprising:doping the wire element; and forming a conductive gate over and alongopposing sides of the wire element.
 11. A method of forming an elementof a microelectronic circuit, comprising: forming an dielectric layerhorizontally over a horizontal semiconductor monocrystalline substrate;forming a sacrificial layer having a horizontal lower surface on ahorizontal upper surface of the dielectric layer, the sacrificial layerbeing of a different material than the dielectric layer; forming aheight-defining layer having a lower surface on a horizontal uppersurface of the sacrificial layer, the height-defining layer being of adifferent material than the sacrificial layer; removing the sacrificiallayer with an etchant that selectively removes the material of thesacrificial layer over the materials of the dielectric layer and theheight-defining layer, to leave a gap between the upper surface of thedielectric layer and the lower surface of the height-defining layer, theheight-defining layer being maintained in a vertical position relativeto the dielectric layer by a support piece on the semiconductormonocrystalline substrate; growing a monocrystalline semiconductormaterial from a nucleation site on the semiconductor monocrystallinesubstrate, the monocrystalline semiconductor material growinghorizontally through the at least part of the gap to form asemiconductor layer with a vertical height thereof being limited by avertical height of the gap.
 12. The method of claim 11, furthercomprising: removing the height-defining layer to expose thesemiconductor layer; and patterning the semiconductor material to have aselect horizontal length.
 13. The method of claim 12, wherein thesemiconductor layer is patterned into a wire element having a selecthorizontal length and having an elongate width.
 14. The method of claim13, further comprising: doping the wire element; and forming aconductive gate over and along opposing sides of the wire element. 15.The method of claim 11, wherein the semiconductor material growsvertically past the dielectric layer before growing horizontally intothe gap.